View 78M6631-IMRF_8865355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-6039; rev 2; 4/12 78m6631 3-phase power- measurement ic data sheet rev 2 1 ds_6631_056 description the teridian? 78m6631 is a highly integrated 3-phase power measurement and monitoring system-on-chip (soc), with a 10 mhz 8051- compatible mpu core and single converter technology? containing a 22-bit delta- sigma converter and 32-bit compute engine (ce). the 78m6631 has been designed specifically for a wide variety of applications requiring 3-phase power and quality measurements. it supports both delta and wye configurations. at the measurement interface, the device provides six analog inputs including three differential current and three voltage for interfacing to current and voltage sensors. the device provides better than 0.5% accuracy over a wide 2000:1 dynamic range. the integrated mpu core and 128 kb of flash memory provide a flexible means of configuration, post- processing, data formatting, interfacing to host processor via a uart or spi interface, or using dio pins for leds or relay control. complete firmware is available from maxim and can be loaded into the ic during manufacturing test. features ? < 0.5% watt accuracy over 2000:1 current range and over temperature ? exceeds iec 62053/ansi c12.20 standards ? voltage reference < 40 ppm/c ? six analog inputs supporting 3-phase voltage and current measurement inputs ? pin- or biselectable delta or wye configuration ? 22-bit delta-sigma adc with independent 32- bit compute engine (ce) ? 8-bit mpu (80515), one clock cycle per instruction with 4 kb mpu xram ? 128 kb flash with security ? 32 khz time base with hardware watchdog timer ? uart, i 2 c, and high-speed slave spi host interface options ? 17 general-purpose 5 v tolerant i/o pins ? packaged in a rohs-compliant (6/6) lead(pb)-free 56-pin tqfn ? application firmware includes (per phase): o true rms current and voltage calculations o active, reactive, apparent, fundamental, and harmonic power calculations o fundamental and harmonic current and voltage calculations o line frequency and power factor calculations o phase compensation ( ? 18 ? at 60 hz) o built-in calibration routines o programmable alarm thresholds o command line (uart) communications o high-speed spi communications teridian is a trademark and single conver ter technology is a registered trademark of maxim integrated products, inc.
78m6631 data sheet ds_6631_056 table of contents 1 hardware functiona l description................................................................................................ ...... 5 1.1 hardware overview .............................................................................................................. ....... 5 1.2 device reset................................................................................................................... ............. 7 1.3 power m anagem ent............................................................................................................... ...... 7 1.3.1 voltage regu lator ............................................................................................................ 7 1.3.2 power fault m anagement................................................................................................ 7 1.4 analog front-e nd (afe) ......................................................................................................... ..... 8 1.4.1 analog current and vo ltage inputs ................................................................................. 8 1.5 digital computati on engine (ce)................................................................................................ .9 1.6 80515 mpu core ................................................................................................................. ...... 10 1.6.1 sfrs ........................................................................................................................... ... 10 1.7 ram ............................................................................................................................ ............... 10 1.8 ioram .......................................................................................................................... ............. 10 1.9 flash .......................................................................................................................... ................ 10 1.9.1 program se curity ........................................................................................................... 10 1.10 oscilla tor ..................................................................................................................... ............... 11 1.11 pll and internal cl ock generation............................................................................................ 11 1.12 real-time cl ock (rtc).......................................................................................................... .... 11 1.13 hardware watc hdog ti mer ........................................................................................................ 11 1.14 temperatur e sensor ............................................................................................................. ..... 12 1.15 general purpos e digital i/o .................................................................................................... ... 12 1.16 d/ y selection pin ................................................................................................................. ...... 12 1.17 eeprom inte rface ............................................................................................................... ..... 12 1.18 spi slav e port................................................................................................................. ........... 12 1.19 test port...................................................................................................................... ............... 13 1.20 uart ........................................................................................................................... .............. 13 1.21 in circuit emulat or (ice ) port ................................................................................................. ... 14 2 electrical sp ecifica tions...................................................................................................... ............. 15 2.1 absolute maxi mum rati ngs ....................................................................................................... 15 2.2 recommended external components....................................................................................... 16 2.3 recommended operati ng conditions........................................................................................ 16 2.4 performance s pecifications ..................................................................................................... .. 17 2.4.1 input logic levels .......................................................................................................... 17 2.4.2 output logic levels ....................................................................................................... 17 2.4.3 power-fault co mparator ............................................................................................... 17 2.4.4 power supply monitor.................................................................................................... 18 2.4.5 supply cu rrent ............................................................................................................... 18 2.4.6 crystal osc illator............................................................................................................ 1 8 2.4.7 temperature sensor...................................................................................................... 19 2.4.8 vref ........................................................................................................................... .. 19 2.4.9 adc converter, v3 p3a referenced ............................................................................. 20 2.5 timing specif ications .......................................................................................................... ....... 21 2.5.1 flash memory ................................................................................................................ 21 2.5.2 eeprom inte rface ........................................................................................................ 21 2.5.3 reset .......................................................................................................................... .21 2.5.4 spi slave port................................................................................................................ 2 2 3 packaging ...................................................................................................................... .................... 23 3.1 56-pin qfn package ............................................................................................................. .... 23 3.2 pinout ......................................................................................................................... ................ 23 3.2.1 56-pin qfn pack age outlin e ........................................................................................ 24 3.2.2 recommended pcb land pattern for the qfn- 56 package ........................................ 25 4 pin descr iptions............................................................................................................... ................. 26 2 rev 2
ds_6631_056 78m6631 data sheet 4.1 power and gr ound pi ns.......................................................................................................... ... 26 4.2 analog pins .................................................................................................................... ............ 26 4.3 digital pins ................................................................................................................... .............. 27 5 i/o equivalent circ uits........................................................................................................ .............. 28 6 ordering info rmation ........................................................................................................... ............. 29 7 contact info rmation............................................................................................................ .............. 29 revision hi story............................................................................................................... ......................... 30 rev 2 3
78m6631 data sheet ds_6631_056 figures figure 1: 78m6631 ic func tional bloc k diagram .................................................................................. ....... 6 figure 2: afe block diagram .................................................................................................... ................... 8 figure 3: functions defined by v1.............................................................................................. ................ 11 figure 4: spi slave port: typical read and write operations ................................................................... 1 3 figure 5: spi slav e port timing................................................................................................ .................. 22 figure 6: pinout fo r qfn-56 package............................................................................................ ............. 23 figure 7: pcb land pattern for qfn-56 package.................................................................................. .... 25 figure 8: i/o equi valent circuits .............................................................................................. ................... 28 tables table 1: spi comm and descri ption............................................................................................... ............. 13 table 2: absolute maximum ratings .............................................................................................. ............ 15 table 3: recommended external components ....................................................................................... ... 16 table 4: recommended operating c onditions...................................................................................... ..... 16 table 5: input logic levels .................................................................................................... ..................... 17 table 6: output logic levels ................................................................................................... ................... 17 table 7: power-fault comparator performance specifications.................................................................. 17 table 8: power supply monitor performance specifications ( bme = 1)...................................................... 18 table 9: supply current pe rformance specifications ............................................................................. .... 18 table 10: crystal oscillator performance s pecifications........................................................................ .... 18 table 11: temperature sensor performance spec ifications ...................................................................... 19 table 12: vref perfor mance specifications...................................................................................... ........ 19 table 13: adc converter pe rformance spec ifications............................................................................. .. 20 table 14: flash memory timing specifications ................................................................................... ....... 21 table 15: eeprom in terface timing.............................................................................................. ............ 21 table 16: re set timing ......................................................................................................... ................... 21 table 17: spi slav e port timing................................................................................................ ................. 22 table 19: power and ground pins................................................................................................ .............. 26 table 20: an alog pi ns .......................................................................................................... ....................... 26 table 21: di gital pins ......................................................................................................... ......................... 27 table 22: orderi ng information ................................................................................................. .................. 29 4 rev 2
ds_6631_056 78m6631 data sheet 1 hardware functional description 1.1 hardware overview the teridian 78m6631 single-chip power measurement and monitoring device integrates all the primary ac measurement and control blocks required to implement the 3-phase power measurement and monitoring system. the 78m6631 includes: ? six input analog front-end (afe) (3 differential current/3 voltage) ? independent digital computation engine (ce) ? 8051-compatible microprocessor (mpu) which exec utes one instruction per clock cycle (80515) ? precision voltage reference ? temperature sensor ? ram and flash memory ? a variety of i/o pins ? communication interfaces: uart, spi, and i 2 c (master) various current sensor technologies are support ed including current transformers (ct), resistive shunts, and rogowski coils. the 32-bit compute engine (ce) of the 78m6631 sequentially process the samples from the analog inputs on pins ia, ib, ic, va, vb, and vc an d performs calculations to measur e active power (watts), reactive power (vars), apparent power (vas), power factor , fundamental power, and harmonic power for three independent phases. rms, fundamental, and harmonic currents and voltages are also computed for each phase. totals are available for most results. figure 1 provides a block diagram of the 78m6631 ic. a detailed de scription of the various functional blocks follows. refer to the applicable firmware description do cument for additional supported functionality. rev 2 5
78m6631 data sheet ds_6631_056 adc converter vref muxp xin xout vref reset v1 uart tx rx digital i /o power fault gndd v3p3a v3p3d volt reg 2.5v to logic tmuxout faultz gnda vbias temp osc (32.768khz) mck pll vref cktest test mode e_ rxtx rtc vbias ice_e test mux v3p3d ce_ prog ck_ce ck_ mpu 80mhz vadc ce multi- purpose io rtm rpulse wpulse dio_4... to tmux spi slave eeprom i /f flash 128kb xram 4kb ce_ data pcsz pclk psdi psdo sdata sdck sfr 80515 mpu emulator e_ tclk e_ rstz e_ rxtx e_ tclk e_ rst rpulse wpulse xram bus 8 16 32 cktest ice_e cktesti pclk psdo pcsz psdi fir vb vc va xpulse ypulse xpulse ypulse ibn icp icn ibp iap ian dio3 dio4/sdck dio5/sdata dio6 dio8 dio9 d/y dio11 dio17 dio24 dio25 dio45 dio47 v3p3sys vbat dio51 dio53 dio30 dio55 dio29 figure 1: 78m6631 ic functional block diagram 6 rev 2
ds_6631_056 78m6631 data sheet 1.2 device reset when the reset pin is pulled high, all digital activity stops. only the oscillator and rtc module continue to run. additionally, all ioram bits are set to their default states. as long as v1 (the input voltage at the power fault block) is greater than vbias, the internal 2.5 v regulator continues to provide power to the digital section. once initiated, the reset mode persists until the rese t timer times out. this occurs in 4096 cycles of the crystal clock after reset goes low, at which ti me the mpu begins execut ing its preboot and boot sequences from address 0x0000. 1.3 power management 1.3.1 voltage regulator the 78m6631 provides an on-chip voltage regulator to create a 2.5 v supply for the digital logic. this regulator can be run off of the v3p3sys or vbat inputs depending upon power availability. 1.3.2 power fault management the 78m6631 provides for both hardware and software controlled power fault management. the v1 pin is connected to a comparator to monitor system power fault conditions. when the input to the comparator falls (v1 < vbias) the device can enter a brownout mode, if supported in firmware and there is sufficient voltage on vbat, that reduces the mpu rate to 32 khz and disables all the measurement front- end circuits. if the overhead on vbat is insufficient to maintain a brownout mode, then the device can also attempt to enter a sleep mode where only rtc functions are active. if there is not sufficient voltage on vbat (or it is not supported), t hen the part enters reset mode when the comparator fails. rev 2 7
78m6631 data sheet ds_6631_056 1.4 analog front-end (afe) the afe functions as a data acquisition system, cont rolled by the mpu. the main blocks in the afe consist of an input multiplexer, a delta-sigma a/ d converter, a fir decimation filter and a voltage reference. the metrology input signals (iap, ian, ibp, ibn, icp, icn, va, vb, vc, and temp) are multiplexed before being sampled by the adc. the adc output is decimated by the fir filter and the results are stored in ram where they c an be accessed by the ce and the mpu. the functionality of the afe is established for variou s system requirements with different ce code. afe programmability includes, but is not limited to: ? input multiplexer settings ? voltage supply and temperature monitor inputs ? adc sampling rate ? fir length/resolution figure 2: afe block diagram 1.4.1 analog current and voltage inputs with all ce code implementations for the 78m6631, pi ns iap, ian, ibp, ibn, icp, icn, va, vb, and vc are analog inputs to the afe for measuring current and voltage. various current sensor technologies can be supported including current transformers , resistive shunts, and rogowski coils. 8 rev 2
ds_6631_056 78m6631 data sheet 1.5 digital computation engine (ce) the ce, a dedicated 32-bit digital signal processor, pe rforms the back-end comput ations. ce calculations include: ? gain and offset compensation ? delay compensation on all channels ? 90? phase shift for var calculations ? frequency measurement ? accumulation for voltage and current rms and power computation ? active, reactive, apparent, fundamental, and harmonic power calculation ? fundamental and harmonic current and voltage calculations ? monitoring of the input signal frequency (for frequency and phase information) ? monitoring of the input signal amplitude (for sag detection) ? temperature acquisition due to the custom nature and complexity of the ce, the ce code is part of the installed firmware and is not modified by the user. contact maxim s upport for more information regarding ce code. rev 2 9
78m6631 data sheet ds_6631_056 1.6 80515 mpu core the 78m6631 includes an 80515 mpu (8-bit, 8051-compatib le) that processes most instructions in one clock cycle. the 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single ma chine cycle (mpu clock cycle). this leads to an 8x average performance improvement (in terms of mips) ov er the intel 8051 device running at the same clock frequency . 1.6.1 sfrs several custom special function registers (sfr) are implemented in the 78m6631?s 80515 mpu. refer to the 78m6631 programmer?s reference manual for more information regarding the mapping of functionality to specific sfr and ioram addresses. 1.7 ram the ce and mpu share a single, general purpose 4kb ram (also referred to as xram) for data. the xram is natively accessible as 32-bit words from the ce and on 8-bit boundaries from the cpu. the xram is accessed by the cpu th rough addresses 0x0000 to 0x0fff. 1.8 ioram the mpu accesses most of its external input and output functionality as well as programmable functionality through memory mapped io (ioram). the ioram is accessed by the cpu as data addresses 0x2000 to 0x20ff. 1.9 flash the 78m6631 includes 128 kb of on-chip flash memory. for read/write access from the cpu, the flash is broken into four 32 kb banks that are managed by sfr settings. for erasing of the flash memory from the cpu, the flash is segmented into individual 1024-byte pages and also controlled by sfr settings. 1.9.1 program security the 78m6631 has functionality to guarantee the security of the user?s mpu and ce program code. when enabled, the security feature limits the ice to global fl ash erase operations only. all other ice operations are blocked. security is enabled by mpu code that is executed in a pre-boot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. 10 rev 2
ds_6631_056 78m6631 data sheet 1.10 oscillator the 78m6631 oscillator drives a stan dard 32.768 khz qua rtz crystal. these crystals are accurate and do not require a high-current oscillato r circuit. the 78m6631 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. the oscillator is powered directly and only from v3 p3d, which therefore must be connected to a dc voltage source not to exceed 4 v. v3p3 v3p3 - 400mv v3p3 - 10mv vbias 0v battery modes normal operation, wdt enabled wdt dis- abled v1 since the oscillator is self-biasing, an external resistor must not be connected across the crystal. 1.11 pll and internal clock generation timing for the device is derived from the 32.768 khz crystal oscillator output. the pll and on-chip timing functions provide several clocks which include: ? the mpu clock (ckmpu) ? the emulator clock (2 x ckmpu) ? the clock for the ce (ckce) ? the delta-sigma adc and fir clock(ckadc, ckfir) these internal clocks can be adjusted for various programmable rates which affect device functionality. refer to the 78m6631 programmer?s reference manual for more information regarding the programmability of the 78m6631 pll and internal clock generation modules. 1.12 real-time clock (rtc) the rtc circuit is driven directly by the crystal oscillator. the rtc co nsists of a counter chain and output registers. the counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year (including leap years). refer to the 78m6631 programmer?s reference manual for more information regarding the use of the 78m6631 rtc. 1.13 hardware watchdog timer in addition to the basic watchdog timer included in the 80515 mpu, an independent, robust, fixed-duration, watchdog timer (wdt) is included in the device. it uses the crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 seconds. when not refreshed on time the wdt overflows, and the part is reset as if the reset pin were pulled high, except that the ioram bits are maintained. 4096 oscillator cycles (or 125 ms) after the wdt overflow, the mpu is launched from program address 0x0000. assert ing ice_e deactivates the wdt. the wdt can also be disabled by connecting the v1 pin to v3p3d. this also deactivates v1 power fault detection. since there is no method in firmware to disable the crystal oscillato r or the wdt, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part is reset to a known state. figure 3: functions defined by v1 rev 2 11
78m6631 data sheet ds_6631_056 1.14 temperature sensor the device includes an on-chip temperature sens or for determining the te mperature of the bandgap reference. the primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system. 1.15 general-purpose digital i/o the 78m6631 includes 17 general-purpose digital i/o pi ns. as inputs, these pins are 5v compatible (no current-limiting resistors are needed). on reset or po wer-up, all dio pins are inputs. their input/output directions are subsequently set by the mpu. the digital i/o pins can be categorized as follows: ? dio3 (1 pin) dio pin ? dio4, dio5 (2 pins) dio/eeprom ? dio6 (1 pin) dio pin (multifunction) ? dio8, dio9, dio11 (3 pins) dio pins ? dio17 (1 pin) dio pin ? dio24, dio25 (2 pins) dio pins ? dio29, dio30 (2 pins) dio pins ? dio45, dio47 (2 pins) dio pins ? dio51 (1 pin) dio pin ? dio53, dio55 (2 pins) dio pins 1.16 d/ y selection pin the d/ y pin selects either the delta or the wye config uration. at power-on, the delta/wye selection register assumes the state of the d/ y pin. the register value can be modified by the software overriding the state of the d/ y pin. 1.17 eeprom interface the 78m6631 provides hardware support for an optional 2-pin or a 3-wire (microwire ? ) eeprom interface. 2-pin eeprom interface the dedicated 2-pin serial interf ace communicates with external eeprom devices. the interface is multiplexed onto the dio4 (sdck) and dio5 (sdata) pins. 3-wire (microwire) eeprom interface a 500 khz three-wire interface, using sdata, s dck and a dio pin for cs, is also available. 1.18 spi slave port the slave spi port communicates directly with the mpu data bus and is able to directly read and write xram and ioram locations. it is also able to send comm ands to the mpu. the interface to the slave port consists of the pcsz, pclk, psdi, and psdo pins. a typical spi transaction is as follows. while pcsz is high, the port is held in an initialized/reset state. during this state, psdo is held in high-z state and all transitions on pclk and psdi are ignored. when pcsz falls, the port begins the transaction on the firs t rising edge of pclk. a transaction consists of an 8-bit command, a 16-bit address, and then one or more bytes of data. the transaction ends when pcsz is raised. some transactions can consist of a co mmand only. the last spi command and address (if part of the command) are available in the ioram. the spi port supports data transfers at up to 1 mbps. the spi commands are described in table 1 and figure 4 illustrates the spi interface read and write timing. microwire is a registered trademark of national semiconductor. 12 rev 2
ds_6631_056 78m6631 data sheet table 1: spi command description command des cription 11xx xxxx addr d0 ... dn output data on psdo is read from ram starting with byte at addr. addr auto increments until pcsz is raised. mpu spi interrupt is generated. 1100 0000 addr d0 ... dn output data on psdo is read from ram starting with byte at addr. addr auto increments until pcsz is raised. no mpu spi interrupt is generated. 10xx xxxx addr d0 ... dn input data on psdi is written to ram starting with byte at addr. addr auto increments until pcsz is raised. mpu spi interrupt is generated. 1000 0000 addr d0 ... dn input data on psdi is written to ram starting with byte at addr. addr auto increments until pcsz is raised. no mpu spi interrupt is generated. cmd addr d0 ... dn cmd and addr are available to the cpu in ioram. d0? dn are ignored. mpu spi interrupt is generated. a15 a14 a1 a0 c0 0 31 x d7 d6 d1 d0 d7 d6 d1 d0 c5c6c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended read . . . serial read a15 a14 a1 a0 c0 0 31 c5c6c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended write . . . serial write d7 d6 d1 d0 d7 d6 d1 d0 x hi z hi z (from host) (from 6531) (from host) (from 6531) figure 4: spi slave port: typical read and write operations since the addresses are in 16-bit format, any type of xram data can be accessed: ce, mpu, or ioram but not sfrs or the 80515-internal register bank. 1.19 test port one out of 16 digital or eight analog signals can be selected to be output on the tmuxout pin. refer to the 78m6631 programmer?s reference manual for more information regarding the use of tmuxout. 1.20 uart the 78m6631 includes one uart (uart0) that can be programmed to communicate with a variety of external devices. the uart is a dedicated 2- wire serial interfaces (no hardware flow control/handshaking), which can communicate at rates up to 38,400 bps. all uart transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 38,400 bps. refer to the 78m6631 programmer?s reference manual for more information regarding t he use of the uart resources. rev 2 13
78m6631 data sheet ds_6631_056 14 rev 2 1.21 in-circuit emulator (ice) port the 78m6631 implements an in-circuit emulator (ice ) port for debug and programming of the device. to enable the use of the port the ice_e pin must be pul led high. in this mode the e_rst, e_tclk, and e_rxtx pins are enabled. contact maxim support for more information regarding the use of the ice interface for device programming and debug.
ds_6631_056 78m6631 data sheet 2 electrical specifications 2.1 absolute maximum ratings table 2 shows the absolute maximum ranges for the device. stresses beyond absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation at these or any other conditions bey ond those indicated under recommended operating conditions (section 2.3 ) is not implied. exposure to absolute-maxim um-rated conditions for extended periods may affect device reliability. all voltages are with respect to gnda. table 2: absolute maximum ratings voltage and current supplies and ground pins v3p3d, v3p3a -0.5 v to 4.0 v gndd -0.5 v to +0.5 v analog output pins vref -10 ma to +10 ma, -0.5 v to (v3p3a + 0.5 v) analog input pins iap, ian, ibp, ibn, icp, icn, va, vb, vc -10 ma to +10 ma -0.5 v to (v3p3a + 0.5 v) xin, xout -10 ma to +10 ma -0.5 v to 3.0 v all other pins configured as digital inputs -10 ma to +10 ma, -0.5 to +6 v configured as digital outputs -15 ma to +15 ma, -0.5 v to (v3p3d + 0.5 v) all other pins -0.5 v to (v3p3d + 0.5 v) temperature and esd stress operating junction temperature (peak, 100 ms) +140c operating junction temperature (continuous) +125c storage temperature -45c to +165c lead temperature (soldering, 10 s) +250c soldering temperature (reflow) +260 ? c esd stress on all pins ? 4 kv rev 2 15
78m6631 data sheet ds_6631_056 2.2 recommended external components table 3: recommended external components name from to function value unit c1 v3p3a agnd bypass capacitor for 3.3 v supply ? 0.1 ? 20% ? f c3 v3p3d dgnd bypass capacitor for v3p3d ? 1.0 ? 30% ? f xtal xin xout 32.768 khz crystal, electrically similar to ecs .327-12.5-17x or vishay xt26t, load capacitance 12.5 pf 32.768 khz cxs xin agnd load capacitor for crystal (depends on crystal specs and board parasitics) 33 ? 10% pf cxl xout agnd load capacitor for crystal (depends on crystal specs and board parasitics) 15 ? 10% pf notes: 1. agnd and dgnd should be connected together. 2. v3p3ds and v3p3a should be connected together. 2.3 recommended operating conditions table 4: recommended operating conditions parameter condition min typ max unit v3p3d, v3p3a: 3.3 v supply voltage (v3p3a and v3p3d must be at the same voltage) normal operation 3.0 3.3 3.6 v operating temperature range -40 +85 oc 16 rev 2
ds_6631_056 78m6631 data sheet 2.4 performance specifications 2.4.1 input logic levels table 5: input logic levels parameter condition min typ max unit digital high-level input voltage 1 , v ih 2 v digital low-level input voltage 1 , v il 0.8 v input pullup current, i il e_rxtx, e_rst, cktest other digital inputs vin = 0 v, ice_e = 1 10 10 -1 0 100 100 +1 ? a ? a ? a input pulldown current, i ih ice_e reset other digital inputs vin = v3p3d 10 10 -1 0 100 100 +1 ? a ? a ? a 1 to reduce power consumption, digital inputs should be below 0.3 v or above 2.5 v to minimize supply current. 2.4.2 output logic levels table 6: output logic levels parameter condition min typ max unit i load = 1 ma v3p3d - 0.4 v digital high-level output voltage v oh i load = 15 ma v3p3d - 0.6 v i load = 1 ma 0 0.4 v digital low-level output voltage v ol i load = 15 ma 0.8 v 2.4.3 power-fault comparator table 7: power-fault comparator performance specifications parameter condition min typ max unit offset voltage: v1 - vbias -20 +15 mv hysteresis current: v1 v in = vbias ? 100 mv 0.8 1.2 ? a response time: v1 + 100 mv overdrive voltage at v1 rising voltage at v1 falling 10 8 37 100 100 ? s ? s wdt disable threshold: v1 - v3p3a -400 -10 mv rev 2 17
78m6631 data sheet ds_6631_056 2.4.4 power supply monitor table 8: power supply monitor performance specifications ( bme = 1) parameter condition min typ max unit load resistor ? 27 45 63 k ? [ m40mhz , m26mhz ] = [00], [10], or [11] fir_len =0 (l=138) fir_len =1 (l=288) (-10%) -48.7 -5.35 (+10%) p v p v lsb value [ m40mhz , m26mhz ] = [01] fir_len =0 (l=186) fir_len =1 (l=384) (-10%) -19.8 -2.26 (+10%) p v p v offset error -200 0 +100 mv 2.4.5 supply current table 9: supply current performance specifications parameter condition min typ max unit v3p3d current (ce off) 4.2 6.35 ma v3p3d current (ce on) 8.4 9.6 ma v3p3a current normal operation, v3p3a = v3p3sys = 3.3 v ckmpu = 614 khz no flash memory write rtm_e =0, eck_dis =1, adc_e =1, ice_e =0 3.3 3.8 ma v3p3d current, write flash normal operation as above, except write flash at maximum rate, ce_e = 0, adc_ e = 0 9.1 12 ma 2.4.6 crystal oscillator table 10: crystal oscillator performance specifications parameter condition min typ max unit maximum output power to crystal 4 crystal connected 1 p w xin to xout capacitance 1 3 pf capacitance to dgnd 1 xin xout rtca_adj = 0 5 5 pf pf 18 rev 2
ds_6631_056 78m6631 data sheet rev 2 19 2.4.7 temperature sensor table 11 shows the performance for the temperature sensor. the lsb values do not include the 8-bit left s hift at ce input. table 11: temperature sensor performance specifications parameter conditio n min typ max unit nominal relationship: n(t) = s n *(t-t n ) + n n , t n = 22oc [ m26mhz, m40mh ] = [00], [01], or [11] fir_len = 0 (l=138) fir_len =1 (l=288) -104 -947 nominal sensitivity (s n ) 3 n 3 l 00107.0s ? ? ? ? ? ? ??? [ m26mhz , m40mhz ] = [10] fir_len =0 (l=186) -255 lsb/oc [ m26mhz, m40mh ] = [00], [01], or [11] fir_len =0 (l=138) fir_len =1 (l=288) 49641 451200 nominal offset (n n ) 4 3 n 3 l 510.0n ? ? ? ? ? ? ?? [ m26mhz , m40mhz ] = [10] fir_len =0 (l=186) 121500 lsb temperature error 2 ? ? ? ? ? ? ? ? ?? n n n t s ntn terr ))(( t n = 22c, t = -40oc to +85oc -10 1 +10 1 oc 1 guaranteed by design; not production tested. 2 n n is measured at t n during measurement calibration and is stored in mpu or ce for use in temperature calculations. 2.4.8 vref table 12 shows the performance specifications fo r v ref. unless otherwise specified, vref_dis = 0. table 12: vref performance specifications parameter conditio n min typ max unit vref output voltage, vref(22) t a = +22oc 1.193 1.195 1.197 v vref chop step 40 mv vref power supply sensitivity ? vref/ ? v3p3a v3p3a = 3.0 to 3.6 v -1.5 +1.5 mv/v vref input impedance vref_dis = 1, vref = 1.3 to 1.7 v 100 k ? vref output impedance cal =1, i load = 10 ? a, -10 ? a 2.5 k ? vnom definition 2 2)22(1)22()22()( 2 tcttct vreftvnom ???? ? v vnom temperature coefficients: tc1 tc2 3.18(52.46- trimt ) -0.444 ? v/oc ? v/c 2 vref(t) deviation from vnom(t) )40,22max( 10 )( )()( 6 ? ? t tvnom tvnomtvref -40 1 +40 1 ppm/oc vref aging ? 25 ppm/year 1 guaranteed by design; not production tested. 2 this relationship describes the nominal behavior of vref at different temperatures.
78m6631 data sheet ds_6631_056 20 rev 2 2.4.9 adc converter, v3p3a referenced table 13 shows the performance specifications for the a dc converter, v3p3a referenced. for this data, fir_len = 0, vref_dis = 0 and lsb values do not include the 9-bit left shift at the ce input. table 13: adc converter performance specifications parameter conditio n min typ max unit recommended input range (v in - v3p3a) -250 +250 mv peak voltage to current crosstalk ) cos( *10 6 vcrosstalk vin vin vcrosstalk ??? v in = 200 mv peak, 65 hz, on va. vcrosstalk = largest measurement on ia or ib -10 1 +10 1 ? v/v thd (first 10 harmonics) 1 : 250 mv-pk 20 mv-pk v in = 65 hz, 64 kpts fft, blackman- harris window ckce = 5 mhz -75 1 -90 1 db db input impedance v in = 65 hz 40 90 k ? temperature coefficient of input impedance v in = 65 hz 1.7 ? /c [ m40mhz , m26mhz ] = [00], [10], or [11] nv/ lsb lsb size 3 3 75.4 25.1 ? ? ? ? ? ? ??? l vv ref lsb l = fir length [ m40mhz , m26mhz ] = [01] nv/ lsb [ m40mhz , m26mhz ] = [00], [10], or [11] lsb digital full scale 3 3 ? ? ? ? ? ? l l = fir length [ m40mhz , m26mhz ] = [01] lsb a dc gain error versus %power supply variation 3.3/33100 /357 10 6 apv vnv nout in pk ? ? v in = 200 mv pk, 65 hz, v3p3a=3.0 v, 3.6 v 50 ppm/% input offset (v in - v3p3a) -10 +10 mv 1 guaranteed by design; not production tested.
ds_6631_056 78m6631 data sheet 2.5 timing specifications 2.5.1 flash memory table 14: flash memory timing specifications parameter condition min typ max unit flash write cycles -40c to +85c 20,000 cycles flash data retention +25c 100 years flash data retention +85c 10 years flash byte write operations between page or mass erase operations 2 cycles write time per byte 42 ? s page erase (1024 bytes) 20 ms mass erase 200 ms 2.5.2 eeprom interface table 15: eeprom interface timing parameter condition min typ max unit ckmpu = 4.9152 mhz, using interrupts 78 khz write clock frequency (i 2 c) ckmpu = 4.9152 mhz, bit-banging dio4/5 150 khz write clock frequency (3-w ire) ckmpu = 4.9152 mhz 500 khz 2.5.3 reset table 16: reset timing parameter condition min typ max unit reset pulse width 5 ? s reset pulse fall time 1 1 ? s 1 guaranteed by design; not production tested. rev 2 21
78m6631 data sheet ds_6631_056 2.5.4 spi slave port table 17: spi slave port timing parameter condition min typ max unit t spicyc pclk cycle time 1 ? s t spilead enable lead time 15 ns t spilag enable lag time 0 ns high 40 t spiw pclk pulse width low 40 ns t spisck pcsz to first pclk fall ignore if pclk is low when pcsz falls 2 ns t spidis disable time 0 ns t spiev pclk to data out 15 ns t spisu data input setup time 10 ns t spih data input hold time 5 ns msb out lsb out msb in lsb in t spicyc t spilead t spilag t spisck t spih t spiw t spiev t spiw t spidis pcsz pclk psdi psdo figure 5: spi slave port timing 22 rev 2
ds_6631_056 78m6631 data sheet 3 packaging 3.1 56-pin qfn package 3.2 pinout figure 6: pinout for qfn-56 package rev 2 23
78m6631 data sheet ds_6631_056 3.2.1 56-pin qfn package outline 24 rev 2
ds_6631_056 78m6631 data sheet 3.2.2 recommended pcb land pattern for the qfn-56 package figure 7: pcb land pattern for qfn-56 package rev 2 25
78m6631 data sheet ds_6631_056 4 pin descriptions 4.1 power and ground pins table 18: power and ground pins name type circuit description gnda p ? analog ground: this pin should be connected directly to the ground plane. gndd p ? digital ground: this pin shoul d be connected directly to the ground plane. v3p3a p ? analog power supply: a 3.3 v power su pply should be connected to this pin, must be the same voltage as v3p3sys. v3p3d p ? system 3.3 v supply. this pin should be connected to a 3.3 v power supply. 4.2 analog pins table 19: analog pins name type circuit description iap, ian, ibp, ibn, icp, icn i 6 line current sense inputs: these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of current sensors. unused pins must be connected to v3p3a . va, vb, vc i 6 line voltage sense inputs: these pins are voltage inputs to the internal a/d converter. typically, they are co nnected to the outputs of resistor dividers. unused pins must be connected to v3p3a. v1 i 7 comparator input: this pin is a volt age input to the internal comparator. the voltage applied to the pin is compared to the internal bias voltage (1.6 v). if the input voltage is above vbias, the comparator output is high (1). if the comparator output is low, a voltage fault occurs. a series 5 k ? resistor should be connected from v1 to the resistor divider. vref o 9 voltage reference for the adc. normally disabled and left unconnected. if enabled, a 0.1 ? f capacitor to v3p3a should be connected to this pin. xin xout i 8 crystal inputs: a 32 khz crystal should be connected across these pins. typically, a 33 pf capacitor is also connected from xin to gnda and a 15 pf capacitor is connected from xout to gnda. it is important to minimize the capacitance between these pins. refer to the crystal manufacturer data sheet for details. if an external clock is used, a 150 mv p-p clock signal should be applied to xin, and xout should be left unconnected. 1) pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified under section 5 i/o equivalent circuits . 26 rev 2
ds_6631_056 78m6631 data sheet rev 2 27 4.3 digital pins table 20: digital pins name t ype circuit description dio3 i/o 3, 4 dedicated dio pin. dio4,dio5,dio6 dio8, dio9, dio11 dio17 dio24, dio25 dio29, dio30 dio45, dio47 dio51, dio53 dio55 i/o 3, 4, 5 multi-use pins, dio. (dio4 = sck, dio5 = sda when configured as eeprom interface; if unused, these pins must be configured as dios and set to outputs by the firmware. d/ y i ? selects either the delta or the wye configuration. pclk psdo pcsz psdi i/o 3, 4, 5 spi port. e_rxtx i/o 1, 4, 5 e_rst i/o 1, 4, 5 e_tclk o 4, 5 port pins (when ice_e pulled high). ice_e i 2 ice enable. when zero, e_rst, e_tclk and e_rxtx seg32 for production units, this pin should be pulled to gnd to disable the emulator port. cktest i/o 3, 4 test clock. tmuxout o 4 digital test multiplexer output. controlled by tmux[3:0]. reset i 2 chip reset: this input pin is used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin should be pulled high. this pin has an internal 30 ? a (typ) current source pulldown. no external reset circuitry is necessary. rx i 3 uart input. if this pin is unused, it must be terminated to v3p3d or gndd. tx o 4 uart output. gndd (pin 55) i 7 enables production test. this pin must be grounded in normal operation. pin types: p = power, o = output, i = input, i/o = input/output. the circuit number denotes the equivalent circuit, as specified in section 5 , i/o equivalent circuits .
78m6631 data sheet ds_6631_056 5 i/o equivalent circuits oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gndd 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull-down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin from vbat 10 40 figure 8: i/o equivalent circuits 28 rev 2
ds_6631_056 78m6631 data sheet rev 2 29 6 ordering information table 21: ordering information part part description (package) flash size packaging order number package marking bulk 78m6631-im/f 78m6631 56-pin qfn, lead(pb)- free 128 kb tape and reel 78m6631-imr/f 78m6631 7 contact information for more information about maxim products or to chec k the availability of t he 78m6631, contact technical support at www.maxim-ic.com/support .
ds_6631_056 78m6631 data sheet 30 rev 2 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrate d products, inc. revision history revision number revision date description pages changed 0 9/11 initial release ? 1 1/12 removed information about programmed devices from table 21. ordering information 29 2 4/12 removed ?-im? from the package marking 29

▲Up To Search▲

Price & Availability of 78M6631-IMRF

	To Download 78M6631-IMRF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .